Field
The disclosed technology relates to the technical filed of microelectronic devices and memories, and more particularly, to a non-volatile ultra-high-density vertical channel-type 3D semiconductor memory device and a method for manufacturing the same.
Description of the Related Technology
Demand for increased storage capacity to meet mass storage requirements drives advances in semiconductor memory technology. One approach is to decrease the size of NAND flash memory to enable increased data storage capability with high-density and low-cost non-volatile flash devices. However, as devices designed with conventional flash technology based on polysilicon floating gates, are scaled down in size using, for example, 20 nm process technology, crosstalk among cells may increase. In addition, extreme ultraviolet (EUV) lithography techniques costs for manufacturing may increase. Therefore, there is a need to develop new memory technology to meet mass storage requirements.
Three-dimensional (3D) memory structures differ from conventional methods for increasing storage density by decreasing the size of the memory cell, by stacking memory cells along a vertical direction (FIG. 1). Samsung Electronics of Korea presented a memory array with dual layers of planar channel obtained by an epitaxial process at the International Electron Devices Meeting (IEDM) in 2006. Toshiba of Japan reported a bit cost scalable (BiCS) memory array with vertical channels obtained by employing a “gate-first” process at VLSI, 2007. Samsung Electronics reported a terabit cell array transistor (TCAT) memory array with vertical channels and a Vertical Stacked Array Transistor memory structure obtained by employing a “gate-last” process at VLSI, 2009. Macronix of Taiwan reported a vertical gate VG-NAND 3D memory with multiple layers of planar channels at VLSI, 2010. International Technology Roadmap for Semiconductors (ITRS) 2001 pointed out that the 3D memory technique is becoming a mainstream technique of the development of flash devices.
Despite advances, issues including reliability of 3D memory devices remain. For example, a 3D memory based on vertical channels, like the memory cell in FIG. 2B, employs a poly silicon channel material regardless of whether a column-shaped channel is employed (FIG. 2A) or a vertical-strip-shaped channel is employed (FIG. 2C). Charge collapse caused by variation of the crystal size of the poly silicon channel and gap traps among crystal grains may significantly decrease carrier mobility. Typically, the carrier mobility of the polysilicon channel is about 1-50 cm2/vs, which is much lower than that of the conventional monocrystal silicon. The excessive lower carrier mobility decreases a reading current of a memory string and limits an access capability of a peripheral circuit. Further, the memory cells stacked along the vertical direction cause different thicknesses of the polysilicon channel for the memory cells at upper and lower portions of the memory string due to a limitation of the etching process. Taking the structure shown in FIG. 3 as an example, the memory cells at the upper portion have a larger channel diameter than the memory cells at the lower portion (d1<d5). When the channel at the lower portion enters a completely depleted state, the channel at the upper portion is still in a partially depleted state. These variations in the storage capability impacts speed of writing and erasing, durability, and may decrease reliability.